98c4d288

By: ValentinHirschi <valentin.hirschi@gmail.com>

W0 intel note: gate 0.4(a) provisional, 0.4(b) borderline (verifier round 1)

Corrects the gate-0.4 verdict in docs/research/fable51_w0_intel_2026-09-27.md:
- 0.4(a) is a provisional PASS. Every timing is void under plan section 7,
  and the SoA-pattern reverse ratio against 4x is undecided.
- 0.4(b) is borderline and conditional. It fires only for a uniform
  alpha >= 0.65 at one thread, or with admission-only thread factors. It
  does not fire at SoA-pattern's own miss/reverse exponents (13.9-22.5% at
  1G). W3.2 moves into W2 as a conservative scope choice, to be re-decided
  on the P-IMP exponents by class.
- The thread factors' bias direction is unknown, not "upper-side".
- The socket-1 foreign-load windows are recomputed.
- The socket1.lock state is recorded with real times.

Adds the fix-round projection cells (gate04b-r2), the lock-state receipt
and their driver scripts.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>